The manufacture of high-voltage transistors in integrated circuits, which is known per se, generally produces optimized transistors for the desired voltage range. This range can extend from more than 10 volts to 150 volts and beyond. A typical application is automobile engineering in which, in addition to its logic circuit elements, switches for the battery voltage levels and for coping with interference pulses (bursts) also have to be provided. These high-voltage transistors can basically be manufactured with processes such as are used for CMOS circuits with application ranges from 3.3 volts to 5 volts. However, this manufacture is costly and expensive because a multiplicity of additional masks and process steps are necessary and/or there is a resulting large space requirement for the high-voltage transistor.
Vertical high-voltage transistors are usually produced in an epitaxy layer whose thickness and concentration has to be optimized for the desired voltage range. The layer thicknesses can quickly be 10 μm or more, which can be implemented only by using complex epitaxy deposition. The necessary buried layer, its doping and formation of contacts with it through the epitaxy layer (sinker) require a number of process steps which are specifically necessary for the high-voltage transistor. In order to optimize the transistor area, i.e. its lateral extent, the thickness of the epitaxy layer has to be adapted to the desired voltage level.
The attempt to manufacture high-voltage transistors as lateral transistors in conjunction with a low-voltage process for logic transistors gives rise to other difficulties. For example, the electrical field strengths have to be allowed for in such a way that a breakdown, which can lead to malfunctions or to the destruction of the integrated circuit, does not occur at the points of maximum field strength concentration. As a rule, this requirement means that a large amount of space is required for the high-voltage transistors, and thus leads to high manufacturing costs.
EP 0 973 205 A2 describes a high-voltage MOS transistor with a drain extension in which the embedding n well has a lower depth underneath the drain extension than underneath the drain which is provided. The depth of the p-conductive well is greater in the area of the drain extension than underneath the drain which is provided. The points of least depth of the n well and greatest depth of the p well are offset with respect to one another.
Document R. Stengi and U. Gösele: “Variation of Lateral Doping—A New Concept to Avoid High Voltage Breakdown of Planar Junctions”, International Electron Devices Meeting, Technical Digest, 1 to 4 December 1985, pages 154 to 157 (XP002013050) describes a masking in order to manufacture a p-conductive well in which additional covers are provided in certain sections between the central area and the edge area of the well which is to be produced.
U.S. Pat. No. 6,455,893 B1 discloses a lateral high-voltage transistor which requires a smaller amount of space because the electrical field strength occurring at the highly doped drain is reduced by means of a drain extension and a field plate with less strong doping. The described transistor can also be used for CMOS processes with less than 1 μm structure width. However, the document indicates that the dielectric strength of the transistor is restricted because the retrograde implantation profile in the edge areas of the drain extension leads to a less suitable doping pattern.